1. Field of the Invention
The present invention relates to a characteristic variation evaluation method for generating a worst-case parameter to evaluate characteristic variations of semiconductor devices; a characteristic variation evaluation unit; and a recording medium for storing a characteristic variation evaluation program, all of semiconductor devices.
2. Description of the Background Art
Fluctuations in semiconductor process conditions stochastically cause circuit performance variations. Such variations have been relatively widened with the shrinking of minimum device size, so that it is getting necessary to estimate performance variations, along with standard performance, in the device development phase.
For instance, there are a method for detecting independent model parameters by a factor analysis or a principal component analysis in order to represent variations of every parameter by the model parameters; and a method for classifying parameters into groups with consideration for their correlation and analyzing sensitivity of each classified group to circuit performance in order to represent circuit performance variations by the sensitivity and the parameter variations.
These methods are both intended to represent variations of characteristic values by the parameter variations, but the use of simulations therein costs much labor. Hence, Technical Report SDM96-122 (1996-11) of the Institute of Electronics, Information and Communication Engineers, for example, provides a method for representing performance variations of basic circuits due to fluctuations in process conditions by circuit model parameters which are obtained by a principal component analysis and a multiple regression analysis, and determining parameters having the highest probability of being the worst case under a certain condition of circuit performance, as parameters representing the worst case (this method is hereinafter referred to as "basic method.")
The features of this conventional basic method are as follows:
(1) To determine parameter values corresponding to the worst case with consideration for a correlation between parameters; PA1 (2) To increase accuracy in probability estimation as compared with a method using corner models; PA1 (3) To determine parameter values by specifying values corresponding to the worst case of circuit performance; and PA1 (4) To reduce the required number of simulations for parameter verification. PA1 .SIGMA..sub.z =A.sup.t.SIGMA..sub.x A/2; PA1 .SIGMA..sub.z is the diagonal matrix. PA1 .mu..sub.p =(b.sup.t.multidot..mu..sub.z +b.sub.0): mean vector of the characteristic value.
Outline of Basic Method
A general flow of the basic method is shown in FIG. 13. First, performance (drain current, circuit delay etc.) of a large number of chips is measured, and a small number of principal parameters (effective channel length, threshold voltage etc.) of model parameters in circuit simulation are extracted from a plurality of chips (step ST1). After eliminating outliers (step ST2), each parameter is applied to distribution (step ST3). Then, a typical chip (typical semiconductor device) giving a standard performance is selected (step ST4) and its principal parameters are extracted as typical parameters (step ST5). At the same time, parameters necessary to represent variations of a characteristic value in the worst case are selected by a partial regression analysis (step ST6) and a multiple regression analysis (step ST7). By adapting the basic method to those selected parameters, a parameter value corresponding to the worst case (worst-case parameter) is determined (step ST8). Finally, the parameters representing the variations of the characteristic value, out of the typical parameters extracted from the typical chip, are replaced by the worst-case parameter to conduct simulation and verification of the worst-case parameter (step ST9).
We will give a further detailed description of each step on the flow chart in FIG. 13. First, parameter extraction at step ST1 is described. The parameters to be extracted at step ST1 are, for example, effective channel length Leff; effective channel width Weff; external resistance RSH; oxide film thickness Tox; threshold voltage Vth; junction capacitance of plane components Cj; and junction capacitance of line components Cjsw. Of the model parameters in circuit simulation, the above parameters are considered as principal parameters having physical connotations and influence on circuit performance such as circuit delay Tpd and drain current Idmax.
Next, outlier elimination at step ST2 is described. At step ST2, parameter sets of chips at least having one outlier are eliminated from the principal parameters in circuit simulation extracted from a plurality of chips. Under present circumstances, there are a method for converting data of each parameter including outliers into an independent variable by a principal component analysis and eliminating outliers until no correlation is found in data of converted variables; and a method for eliminating outliers by referring to conversion and distribution of each parameter.
The former method by the principal component analysis is, for example, shown in FIGS. 14 and 15. The vertical axis denotes a second principal component and the horizontal axis denotes a first principal component. In FIG. 14, those principal components are correlated because of outliers mixed therein. By eliminating the outliers, a distribution of plots is rounded as shown in FIG. 15, in which the principal components are uncorrected. Such operation is performed on certain principal components for each parameter to eliminate outliers.
Next, application to distribution at step ST3 is described. At step ST3, characteristic values and parameters are applied to suitable probability distribution. Assuming in general that a random variable influenced by various non-specific factors approximately has a normal distribution, a characteristic value is applied to normal distribution and parameters are applied to multivariate normal distribution. FIG. 16 shows a characteristic value and principal parameters applied to normal distribution. As shown, the parameters and the characteristic value almost have a normal distribution, and there is a correlation between the parameters as shown in FIG. 17.
Next, chip selection for typical parameter selection at step ST4 is described. First, alternatives are narrowed down to chips whose characteristic values are about average in distribution. As necessary, the principal parameters may also be used to narrow down the alternatives. Then, a chip whose principal model parameters have the highest probability density is selected as a typical chip from which all model parameters with typical values in circuit simulation are extracted. At step ST5, predetermined parameters (Leff, Vth etc.) of the typical chip (semiconductor device) are extracted as typical parameters.
Next, parameter selection by the partial regression analysis at step ST6 is described. At step ST6, it is checked whether one certain parameter which is considered to contribute to the variations of the characteristic value includes a component other than the components representing the characteristic value. That is, the partial regression analysis reveals a contribution of a certain parameter to the characteristic values.
Next, multiple regression analysis at step ST7 is described by which a contribution of a parameter set to the characteristic value is confirmed. At step ST7, the degree of correlation between measured values and values of linear regression equations calculated from the parameter set selected by the partial regression analysis, is checked. This analysis confirms to what degree the selected parameters can represent the variations of the characteristic value.
Next, a method for determining the worst-case MOSFET model parameter at step ST8 is described. A variable characteristic value p (circuit delay time, current driving capability etc.) is considered as a random variable having a certain probability distribution. Using a model parameter x in circuit simulation having a large contribution to variations of the characteristic value p, the variations of the characteristic value p are generally expressed as p=F(x)+e, where p is the random variable vector of the characteristic value; x is the random variable vector of the parameter; and e is the error vector. In the present specification, a constant is also included in the concepts of vectors as a vector with one element, so the description in the case of a constant will be omitted.
FIGS. 18A to 18D show that current driving capability Idmax as the characteristic value p can be well represented by the effective channel length Leff, the effective channel width Weff, the external resistance RSH, the oxide film thickness Tox, and the threshold voltage Vth. FIG. 18A shows a correlation between the parameters Leff, Vth, Tox and the characteristic value Idmax; FIG. 18B shows a correlation between the parameter Tox and the characteristic value Idmax; FIG. 18C shows a correlation between the parameters Leff, Weff, RSH, Vth, Tox and the characteristic value Idmax; and FIG. 18D shows a correlation between the parameters Weff, Vth, Tox and the characteristic value Idmax. Assuming that the variations of the characteristic value are considerably small, the characteristic value p can be expressed by a linear combination as follows: EQU p=.beta..sup.t x+.beta..sub.0 +e (1)
where .beta. is the partial regression coefficient vector or matrix in the multiple regression analysis; and t is the transposition symbol.
FIG. 19 shows that the current driving capability Idmax as the characteristic value p can be well represented by a linear combination of the effective channel length Leff, the effective channel width Weff, the external resistance RSH, the oxide film thickness Tox, and the threshold voltage Vth. Suppose that the model parameters in circuit simulation which can well represent the variations of the characteristic value have a certain multidimensional distribution. For example, multivariate normal distribution of x.apprxeq.N(.mu..sub.x, .SIGMA..sub.x) is assumed in this case. Then, the probability density function can be expressed as: ##EQU1##
where .mu..sub.x is the mean vector of x; and .SIGMA..sub.x is the variance-covariance matrix of x.
Since there is a correlation between the parameters as previously described, the parameters are applied to multivariate normal distribution which can consider a linear correlation between the parameters. In general, a linear combination of random variables having a normal distribution shows a normal distribution, so p.apprxeq.N(.mu..sub.p, .SIGMA..sub.p). By applying a suitable normal direct matrix A to x, Z can have an independent normal distribution: EQU Z=A.sup.t X (2)
From Equation (1), the characteristic value p can be expressed by a linear combination of Z: EQU C=b.sup.t Z+b.sub.0 +e (3)
Further, the probability density function of Z is given by: ##EQU2##
where
Ignoring the error term e, consider C as a constant value corresponding to the worst/best-case characteristic value. Then, Equation (3) can be considered as an equation restricted on Z: EQU b.sup.t.multidot.Z=C-b.sub.O (5)
The principle component Z that satisfies Equation (5) and maximizes the logarithmic probability density function of Equation (4), is given by: EQU z=.mu..sub.x +(.SIGMA..sub.z.multidot.b).sup.-1.multidot.(p-.mu..sub.p) (6)
where
Further, from Equation (2), a worst-case parameter x.sub.w can be expressed as:
x.sub.w =.mu..sub.x +(.SIGMA..sub.x.multidot.B).multidot.(B.sup.t.multidot..SIGMA..sub.x B).sup.-1.multidot.(p-.mu..sub.p) (7)
where EQU B=(Ab) (8)
If a characteristic value with desired yield is inserted into Equation (7), model parameters in circuit simulation corresponding to the worst/best-case characteristic value can be uniquely obtained.
Next, verification results of the worst-case parameter at step ST9 is described. In a 0.35-.mu.m CMOS process, verification of the basic method is conducted. To obtain parameters, firstly with a delay time Tpd of an inverter chain as a characteristic value, the basis method is applied to the current driving capabilities Idmax, the junction capacitances of plane components Cj, and the junction capacitances of line components Cjsw of both N- and P-channels, to obtain respective worst/best-case values. Secondly with the current driving capabilities Idmax as a characteristic value, the other parameter values are obtained.
According to the partial regression analysis with the current driving capabilities Idmax, the junction capacitances of plane components Cj, and the junction capacitances of line components Cjsw of both NMOS and PMOS transistors as a parameter set and the basic circuit as a characteristic value, it is found that the partial regression coefficient of the junction capacitance Cj of the PMOS transistor is considerably low. That junction capacitance Cj is, however, left as one of parameters representing the worst/best case in order to maintain a balance of parameters between the channels. As a result, the junction capacitance Cj of the PMOS transistor becomes about a mean value.
FIG. 20 shows the results of the multiple regression analysis with the delay time Tpd of an inverter chain as a characteristic value and the current driving capabilities Idmax, the junction capacitances of plane components Cj, the junction capacitances of line components Cjsw of both N- and P-channels as explanatory variables.
The analysis shows that in the basic circuit, the inverter chain has a correlation coefficient of 0.90 and the other circuits have a correlation coefficient of 0.87 or more. This indicates that the variations in the basic circuit can be expressed in a linear form of the current driving capabilities Idmax, the junction capacitances of plane components Cj, and the junction capacitances of line components Cjsw of both N- and P-channels.
Next, the partial regression analysis is conducted with the effective channel length Leff, the effective channel width Weff, the oxide film thickness Tox, the external resistance RSH, and the threshold voltage Vth as a parameter set, and the current driving capabilities Idmax of both NMOS and PMOS transistors, Leff of 0.35, and Weff of 10 .mu.m as a characteristic value.
The effective channel width Weff is excluded from the parameters representing the worst/best case because of its considerably low partial regression coefficient. The oxide film thickness Tox is also excluded because of its small variations and its correlation with the threshold voltage Vth. The other parameters have a high partial regression coefficient with respect to the current driving capability Idmax.
FIG. 21 shows the results of the multiple regression analysis with the current driving capability Idmax of the NMOS transistor as a characteristic value and the effective channel length Leff, the external resistance RSH, and the threshold voltage Vth as explanatory variables. Based on the above result, in both NMOS and PMOS transistors, the effective channel length Leff, the external resistance RSH, and the threshold voltage Vth are used as parameters representing the worst/best-case current driving capability Idmax.
FIG. 22 shows a comparison between measured values and simulated values of the worst/best-case current driving capability Idmax (-3.sigma., -2.sigma., -.sigma., .sigma., 2.sigma., 3.sigma.). The simulations are performed by using the parameter value calculated by the basic method. In both NMOS and PMOS transistors, the effective channel length Leff, the external resistance RSH, the threshold voltage Vth, the junction capacitance of plane components Cj, and the junction capacitance of line components Cjsw are used as parameters representing the worst/best-case circuit performance. The other parameters are typical parameters extracted at step ST5. FIG. 23 shows errors of variations between measured values and simulated values of the basic circuit. The variations of the simulated values obtained from the above parameters almost agree with the variations of the measured values.
To make the conventional problems easy to understand, we will recapitulate step ST8 of calculating the worst-case parameter after step ST10 in FIG. 13. Step ST8 roughly includes: step ST11 of calculating sensitivity; and step ST12 of calculating the worst-case parameter as shown in FIG. 24. In the foregoing description, sensitivity B is obtained by the principal component analysis and the worst-case parameter x.sub.w is obtained from Equation (7). Alternatively, the sensitivity can be calculated as follows: First, a product unit having standard characteristics is determined by the parameter x and the characteristic value p, and parameters representing the characteristics of the product unit are extracted by a structural formula showing product characteristics. Then, sensitivity of these parameters to the characteristic value is analyzed to calculate a partial differential coefficient B[.differential.pi/.differential.xj] (i=1, 2, . . . , k, j=1, 2, . . . , n).
The parameters used for the generation of the worst-case parameter at step ST8 is empirically selected at step ST10 through the partial regression analysis at step ST6 and the multiple regression analysis at step ST7.
In the aforementioned conventional characteristic variation evaluation method of semiconductor devices, the parameters used for the generation of the worst-case parameter are selected by repeating much trial and error based on experiences. This complicates the procedure for generating the worst-case parameter and consumes much time.
Another problem is that the calculation of sensitivity used for the generation of the worst-case parameter requires the principal component analysis. This complicates calculation.
Another problem is that it is difficult to increase accuracy of the worst-case parameter.
Another problem is that calculation becomes complicated when the number of parameters used for the generation of the worst-case parameter is different from the number of characteristic values.
Another problem is that the calculation of the worst-case parameter is complicated and time consuming.